Transistor models, such as field effect transistor (FET) models, are critical in achieving reliable performance from circuit designs that include transistors. One significant purpose of a transistor model, such as a Metal-Oxide Semiconductor FET (MOSFET) model, is to verify circuit performance in simulation prior to actual fabrication of the circuit. The accuracy of a transistor model can be determined by how closely circuit simulation results, i.e., the predicted operation of the circuit, approximates circuit data measured from the fabricated circuit. For circuit simulation results to closely approximate measured circuit data, the transistor model requires accurate model parameters, such as current vs. voltage (I-V) and capacitance vs. voltage (C-V) model parameters.
Transistor model parameters, such as I-V and C-V model parameters, can be extracted from I-V and C-V measurements made from respective I-V and C-V test structures. For the extracted I-V and C-V model parameters to accurately predict transistor behavior, it is important that the transistor model include accurate dimensions of the I-V and C-V test structures. In particular, it is important for gate length, which is a gate critical dimension (CD), of the I-V test structure to match the gate length of the C-V test structure in the transistor model. However, process variations, such as variations in gate polysilicon (poly) density, etchant distribution variations during gate etching, and variations in diffraction during photolithographic processing, can cause the fabricated gate lengths of the I-V and C-V test structures to be different. If the transistor model is not adjusted for the difference in gate length between the I-V and C-V test structures, the transistor model may not provide accurate circuit simulation results.